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ltc3417a 1 3417afc typical a pplica t ion fea t ures a pplica t ions descrip t ion dual synchronous 1.5a/1a 4mhz step-down dc/dc regulator the ltc ? 3417a is a dual constant frequency, synchronous step-down dc/dc converter. intended for medium power applications, it operates from a 2.25v to 5.5v input volt- age range and has a constant programmable switching frequency, allowing the use of tiny, low cost capacitors and inductors 2mm or less in height. each output voltage is adjustable from 0.8v to 5v. internal, synchronous, low r ds(on) power switches provide high effciency without the need for external schottky diodes. a user selectable mode input allows the user to trade off ripple voltage for light load effciency. burst mode ? operation provides high effciency at light loads, while pulse skip mode provides low ripple noise at light loads. a phase mode pin allows the second channel to operate in-phase or 180 out-of-phase with respect to channel 1. out-of-phase operation produces lower rms current on v in and thus a lower rms derating on the input capacitor. to further maximize battery life, the p-channel mosfets are turned on continuously in dropout (100% duty cycle) and both channels draw a total quiescent current of only 125a. in shutdown, the device draws <1a. out2 effciency (burst mode operation) n high effciency: up to 95% n 1.5a/1a guaranteed minimum output current n synchronizable to external clock n no schottky diodes required n programmable frequency operation: 1.5mhz or adjustable from 0.6mhz to 4mhz n low r ds(on) internal switches n short-circuit protected n v in : 2.25v to 5.5v n current mode operation for excellent line and load transient response n 125a quiescent current in sleep mode n ultralow shutdown current: i q < 1a n low dropout operation: 100% duty cycle n power good output n phase pin selects 2nd channel phase relationship with respect to 1st channel n internal soft-start with individual run pin control n available in small thermally enhanced (5mm 3mm) dfn and 20-lead tssop packages n gps/navigation n digital cameras n pc cards n wireless and dsl modems n general purpose point of load dc/dc l , lt, ltc, ltm and burst mode are registered trademarks and hot swap and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 6144194. freq sw1 run1 v fb1 i th1 sw2 run2 v fb2 i th2 v in ltc3417a gnd 10f 1.5h 2.2h 22pf 511k 22pf 866k v in v in 412k 412k 22f 5.9k 2.87k 2200pf 6800pf 3417 ta01 47f v out1 1.8v 1.5a v out2 2.5v 1a v in 2.5v to 5.5v load current (a) 0.001 70 efficiency (%) 90 95 100 0.01 0.1 1 3417 ta01a 85 80 75 power loss (w) 0.001 0.01 0.1 1 10 0.0001 efficiency refer to figure 4 power loss v in = 3.6v v out = 2.5v freq = 1mhz
ltc3417a 2 3417afc a bsolu t e maxi m u m r a t ings v in1 , v in2 voltages ...................................... C 0.3v to 6v sync/mode, sw1, sw2, run1, run2, v fb1 , v fb2 , phase, freq, i th1 , i th2 voltages............... C 0.3v to (v in1 /v in2 + 0.3v) v in1 C v in2 , v in2 C v in1 .......................................... 0.3v (note 1) 16 15 14 13 12 11 10 9 17 1 2 3 4 5 6 7 8 pgnd1 sw1 phase gnda freq pgood sw2 sync/mode run1 v in1 i th1 v fb1 v fb2 i th2 run2 v in2 top view dhc package 16-lead (3mm 5mm) plastic dfn t jmax = 125c, ja = 43c/w exposed pad (pin 17) is pgnd2/gndd, must be soldered to pcb fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 gndd run1 v in1 i th1 v fb1 v fb2 i th2 run2 v in2 pgnd2 gndd pgnd1 sw1 phase gnda freq pgood sw2 sync/mode pgnd2 21 t jmax = 125c, ja = 38c/w exposed pad (pin 21) is pgnd2/gndd, must be soldered to pcb p in c on f igura t ion or d er in f or m a t ion lead free finish tape and reel part marking package description temperature range ltc3417aedhc#pbf ltc3417aedhc#trpbf 3417a 16-lead (3mm 3mm) plastic dfn C40c to 85c ltc3417aefe#pbf ltc3417aefe#trpbf ltc3417aefe 20-lead plastic tssop C40c to 85c ltc3417aife#pbf ltc3417aife#trpbf ltc3417aife 20-lead plastic tssop C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ pgood voltage ........................................... C 0.3v to 6v operating ambient t emperature range (note 2) .................................................. C 40c to 85c junction temperature (notes 7, 8) ...................... 125c storage temperature range ................... C 65c to 125c symbol parameter conditions min typ max units v in1 , v in2 operating voltage range v in1 = v in2 2.25 5.5 v i fb1 , i fb2 feedback pin input current (note 3) 0.1 a v fb1 , v fb2 feedback voltage (note 3) 0.784 0.8 0.816 v ?v linereg reference voltage line regulation. %/v is the percentage change in v out with a change in v in v in = 2.25v to 5v (note 3) 0.04 0.2 %/v v loadreg output voltage load regulation i th1 , i th2 = 0.36v (note 3) i th1 , i th2 = 0.84v (note 3) 0.02 C0.02 0.2 C0.2 % % g m(ea) error amplifer transconductance i th1 , i th2(pinload) = 5a (note 3) 1400 s elec t rical charac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 3.6v unless otherwise specifed. (note 2)
ltc3417a 3 3417afc e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3417ae is guaranteed to meet specifed performance from 0c to 85c. specifcations over the C40c to 85c operating ambient temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3417ai is guaranteed to meet performance specifcations over the C40c to 85c operating temperature range. note 3: the ltc3417a is tested in feedback loop which servos v fb1 to the midpoint for the error amplifer (v ith1 = 0.6v) and v fb2 to the midpoint for the error amplifer (v ith2 = 0.6v). note 4: total supply current is higher due to the internal gate charge being delivered at the switching frequency. the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 3.6v unless otherwise specifed. (note 2) note 5: switch on-resistance is guaranteed by design and test correlation on the dhc package and by fnal test correlation on the fe package. note 6: variable frequency operation with resistor is guaranteed by design but not production tested and is subject to duty cycle limitations. note 7: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the specifed maximum operating junction temperature may impair device reliability. note 8: t j is calculated from the ambient temperature, t a , and power dis- sipation, p d , according to the following formula: ltc3417aedhc: t j = t a + (p d ? 43c/w) ltc3417aefe: t j = t a + (p d ? 38c/w) symbol parameter conditions min typ max units i s input dc supply current (note 4) active mode v fb1 = v fb2 = 0.75v, v sync/mode = v in , v run1 = v run2 = v in 400 600 a half active mode (v run2 = 0v, 1.5a only) v fb1 = 0.75v, v sync/mode = v in , v run1 = v in 260 400 a half active mode (v run1 = 0v, 1a only) v fb2 = 0.75v, v sync/mode = v in , v run2 = v in 260 400 a both channels in sleep mode v fb1 = v fb2 = 1v, v sync/mode = v in , v run1 = v run2 = v in 125 250 a shutdown v run1 = v run2 = 0v 0.1 1 a f osc oscillator frequency v freq = v in v freq : r t = 143k v freq : resistor (note 6) 1.2 0.85 1.5 1 1.8 1.25 4 mhz mhz mhz i lim1 peak switch current limit on sw1 (1.5a) 2.1 2.5 a i lim2 peak switch current limit on sw2 (1a) 1.4 1.7 a r ds(on)1 sw1 top switch on-resistance (1.5a) sw1 bottom switch on-resistance v in1 = 3.6v (note 5) v in1 = 3.6v (note 5) 0.088 0.084 r ds(on)2 sw2 top switch on-resistance (1a) sw2 bottom switch on-resistance v in2 = 3.6v (note 5) v in2 = 3.6v (note 5) 0.16 0.15 i sw1(lkg) switch leakage current sw1 (1.5a) v in1 = 6v, v ith1 = 0v, v run1 = 0v 0.01 1 a i sw2(lkg) switch leakage current sw2 (1a) v in2 = 6v, v ith2 = 0v, v run2 = 0v 0.01 1 a v uvlo undervoltage lockout threshold v in1 , v in2 ramping down v in1 , v in2 ramping up 1.9 1.95 2.07 2.12 2.2 2.25 v v t pgood threshold for power good. percentage deviation from v fb steady state (typically 0.8v) v fb1 or v fb2 ramping up, v sync/mode = 0v v fb1 or v fb2 ramping down, v sync/mode = 0v C6 C6 % % r pgood power good pull-down on-resistance 160 300 v run1 , v run2 run1, run2 threshold 0.3 0.85 1.5 v v phase phase threshold high-cmos levels v in C0.5 v phase threshold low-cmos levels 0.5 v i run1 , i run2 , i phase , i sync/mode run1, run2, phase and sync/mode leakage current v in = 6v, v pvin = 3v 0.01 1 a vtl sync/mode sync/mode threshold voltage low 0.5 v vth sync/mode sync/mode threshold voltage high v in C0.5 v vth freq freq threshold voltage high v in C0.5 v
ltc3417a 4 3417afc typical p er f or m ance c harac t eris t ics out1 burst mode operation out1 pulse skipping mode operation out1 forced continuous mode operation out2 burst mode operation out2 pulse skipping mode operation out2 forced continuous mode operation out1 effciency vs load current out2 effciency vs load current out1 effciency vs v in (burst mode operation) 3417 g01 v in = 3.6v v out = 1.8v i load = 100ma refer to figure 4 i l 250ma/div v out 20mv/div 2s/div 3417 g02 v in = 3.6v v out = 1.8v i load = 100ma refer to figure 4 i l 250ma/div v out 20mv/div 2s/div 3417 g03 v in = 3.6v v out = 1.8v i load = 100ma refer to figure 4 i l 250ma/div v out 20mv/div 2s/div 3417 g04 v in = 3.6v v out = 2.5v i load = 60ma refer to figure 4 i l 250ma/div v out 20mv/div 2s/div 3417 g05 v in = 3.6v v out = 2.5v i load = 60ma refer to figure 4 i l 250ma/div v out 20mv/div 2s/div 3417 g06 v in = 3.6v v out = 2.5v i load = 60ma refer to figure 4 i l 250ma/div v out 20mv/div 2s/div load current (a) 70 efficiency (%) 80 85 95 100 0.001 0.1 1 10 3417 g07 60 0.01 90 75 65 v in = 2.5v v out = 1.8v burst mode operation pulse skip forced continuous refer to figure 4 0.001 0.1 1 10 0.01 load current (a) 80 efficiency (%) 90 100 3417 g08 70 75 85 95 65 60 v in = 3.6v v out = 2.5v burst mode operation pulse skip forced continuous refer to figure 4 v in (v) 2 2.5 3.5 4.5 5.5 efficiency (%) 90 95 100 3417 g09 85 80 3 4 5 75 70 v out = 1.8v i load = 1.4a i load = 460ma refer to figure 4
ltc3417a 5 3417afc typical p er f or m ance c harac t eris t ics out2 effciency vs v in (pulse skipping mode) load step out1 load step out2 effciency vs frequency out1 effciency vs frequency out2 r ds(on) vs v in out1 r ds(on) vs v in out2 frequency vs v in frequency vs temperature v in (v) 2 2.5 efficiency (%) 90 95 100 3417 g10 85 80 3 3.5 4 4.5 5 5.5 75 70 v out = 2.5v refer to figure 4 i load = 800ma i load = 250ma v in = 3.6v v out = 1.8v i load = 0.25a to 1.4a refer to figure 4 i out1 500ma/div v out1 100mv/div 3417 g11 100s/div v in = 3.6v v out = 2.5v i load = 0.25a to 0.8a refer to figure 4 i out2 500ma/div v out2 100mv/div 3417 g12 100s/div frequency (mhz) 0 82 efficiency (%) 84 86 88 90 92 94 1 2 3 4 3417 g13 5 t a = 27c v in = 3.6v v out = 1.8v i out = 300ma frequency (mhz) 0 60 efficiency (%) 65 70 75 80 85 90 1 2 3 4 3417 g14 t a = 27c v in = 3.6v v out = 2.5v i out = 100ma v in (v) 2 2.5 0.080 r ds(on) () 0.090 0.105 3 4 4.5 3417 g15 0.085 0.100 0.095 3.5 5 5.5 t a = 27c p-channel switch n-channel switch v in (v) 2 r ds(on) () 0.18 0.19 0.20 3.5 4.5 3417 g16 0.17 0.16 2.5 3 4 5 5.5 0.15 0.14 t a = 27c p-channel switch n-channel switch v in (v) 2 frequency variation (%) 0 2 4 5 5.5 3417 g17 ?4 ?10 2.5 3 3.5 4 4.5 6 ?2 ?6 ?8 freq = 143k to ground freq = v in temperature (?c) ?50 frequency variation (%) 5 10 15 25 75 3417 g18 0 ?5 ?25 0 50 100 125 ?10 ?15 freq = 143k to ground freq = v in
ltc3417a 6 3417afc p in func t ions run1 (pin 1/pin 2): enable for 1.5a regulator. when at logic 1, 1.5a regulator is running. when at 0v, 1.5a regulator is off. when both run1 and run2 are at 0v, the part is in shutdown. v in1 (pin 2/pin 3): supply pin for p-channel switch of 1.5a regulator. i th1 (pin 3/pin 4): error amplifer compensation point for 1.5a regulator. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is 0v to 1.5v. v fb1 (pin 4/pin 5): receives the feedback voltage from external resistive divider across the 1.5a regulator output. nominal voltage for this pin is 0.8v. v fb2 (pin 5/pin 6): receives the feedback voltage from external resistive divider across the 1a regulator output. nominal voltage for this pin is 0.8v. i th2 (pin 6/pin 7): error amplifer compensation point for 1a regulator. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is 0v to 1.5v. run2 (pin 7/pin 8): enable for 1a regulator. when at logic 1, 1a regulator is running. when at 0v, 1a regula - tor is off. when both run1 and run2 are at 0v, the part is in shutdown. v in2 (pin 8/pin 9): supply pin for p-channel switch of 1a regulator and supply for analog circuitry. sync/mode (pin 9/pin 12): combination mode selection and oscillator synchronization pin. this pin controls the op- eration of the device. when the voltage on the sync/mode pin is >(v in C 0.5v), burst mode operation is selected. when the voltage on the sync/mode pin is <0.5v, pulse skipping mode is selected. when the sync/mode pin is held at v in /2, forced continuous mode is selected. the oscillation frequency can be synchronized to an external oscillator applied to this pin. when synchronized to an external clock, pulse skip mode is selected. sw2 (pin 10/pin 13): switch node connection to the inductor for the 1a regulator. this pin swings from v in2 to pgnd2. pgood (pin 11/pin 14): power good pin. this common drain-logic output is pulled to gnd when the output voltage of either regulator is C 6% of regulation. if either run1 or run2 is low (the respective regulator is in sleep mode and therefore the output voltage is low), then pgood refects the regulation of the running regulator. freq (pin 12/pin 15): frequency set pin. when freq is at v in , internal oscillator runs at 1.5mhz. when a resistor is connected from this pin to ground, the internal oscillator frequency can be varied from 0.6mhz to 4mhz. gnda (pin 13/pin 16): analog ground pin for internal analog circuitry. phase (pin 14/pin 17): selects 1a regulator switching phase with respect to 1.5a regulator switching. set to v in , the 1.5a regulator and the 1a regulator are in phase. when phase is at 0v, the 1.5a regulator and the 1a regulator are switching 180 degrees out-of-phase. sw1 (pin 15/pin 18): switch node connection to the inductor for the 1.5a regulator. this pin swings from v in1 to pgnd1. pgnd1 (pin 16/pin 19): ground for sw1 n-channel driver. pgnd2, gndd (pins 1,10,11,20): tssop package only. ground for sw2 n-channel driver and digital ground for circuit. exposed pad (pin 17/pin 21): pgnd2, gndd. ground for sw2 n-channel driver and digital ground for circuit. the exposed pad must be soldered to pcb ground. (dfn/tssop)
ltc3417a 7 3417afc f unc t ional diagra m ? + ? + ? + ? + ? + i th limit i th1 1.5a regulator 1a regulator v b 0.752v 0.752v v b 0.848v 0.848v v in2 v in1 sw1 pgnd1 pgood phase slope compensation anti-shoot- through oscillator logic ? + ? + v fb1 ? + ? + ? + ? + ? + ? + ? + run1 run2 sync/mode v fb2 i th2 v in2 3417 bd freq pgnd2 sw2 slope compensation anti-shoot- through i th limit logic voltage reference
ltc3417a 8 3417afc the ltc3417a uses a constant frequency, current mode architecture. both channels share the same clock frequency. the phase pin sets whether the channels are running in-phase or out of phase. the operating frequency is de- termined by connecting the freq pin to v in for 1.5mhz operation or by connecting a resistor from freq to ground for a frequency from 0.6mhz to 4mhz. to suit a variety of applications, the sync/mode pin allows the user to trade off noise for effciency. the output voltages are set by external dividers returned to the v fb1 and v fb2 pins. an error amplifer compares the divided output voltage with a reference voltage of 0.8v and adjusts the peak inductor current accordingly. undervoltage comparators will pull the pgood output low when either output voltage is 6% below its targeted value. main control loop for each regulator, during normal operation, the p-chan - nel mosfet power switch is turned on at the beginning of a clock cycle when the v fb voltage is below the refer - ence voltage. the current into the inductor and the load increases until the current limit is reached. the switch turns off and energy stored in the inductor fows through the bottom n-channel mosfet switch into the load until the next clock cycle. the peak inductor current is controlled by the voltage on the i th pin, which is the output of the error amplifer. this amplifer compares the v fb pin to the 0.8v reference. when the load current increases the v fb voltage decreases slightly below the reference. this decrease causes the er - ror amplifer to increase the i th voltage until the average inductor current matches the new load current. the main control loop is shut down by pulling the run pin to ground. a digital soft-start is enabled after shutdown, which will slowly ramp the peak inductor current up over 1024 clock cycles. low current operation three modes are available to control the operation of the ltc3417a at low currents. each of the three modes automatically switch from continuous operation to the selected mode when the load current is low. to optimize effciency, burst mode operation can be selected. when the load is relatively light, the ltc3417a automatically switches into burst mode operation in which the pmos switches operate intermittently based on load demand. by running cycles periodically, the switching losses, which are dominated by the gate charge losses of the power mosfets, are minimized. the main control loop is interrupted when the output voltage reaches the desired regulated value. the hysteresis voltage comparator trips when i th is below 0.24v, shutting off the switch and reducing the power. the output capacitor and the induc - tor supply the power to the load until i th exceeds 0.31v, turning on the switch and the main control loop which starts another cycle. for lower output voltage ripple at low currents, pulse skipping mode can be used. in this mode, the ltc3417a continues to switch at constant frequency down to very low currents, where it will begin skipping pulses used to control the power mosfets. finally, in forced continuous mode, the inductor current is constantly cycled creating a fxed output voltage ripple at all output current levels. this feature is desirable in telecom- munications since the noise is a constant frequency and is thus easy to flter out. another advantage of this mode is that the regulator is capable of both sourcing current into a load and sinking some current from the output. the mode selection for the ltc3417a is set using the sync/mode pin. the sync/mode pin sets the mode for both the1a and the 1.5a step-down dc/dc converters. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases to 100%. in this dropout condition, the pmos switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal p-channel mosfet and inductor. low supply operation the ltc3417a incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below about 2.07v to prevent unstable operation. o pera t ion
ltc3417a 9 3417afc applica t ions in f or m a t ion figure 1. frequency vs r t a general ltc3417a application circuit is shown in figure 4. external component selection is driven by the load requirement, and begins with the selection of the inductors l1 and l2. once l1 and l2 are chosen, c in , c out1 and c out2 can be selected. operating frequency selection of the operating frequency is a tradeoff between effciency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves effciency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency, f o , of the ltc3417a is determined by pulling the freq pin to v in for 1.5mhz operation or by connecting an external resistor from freq to ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: r t 1.61 ? 10 11 f o ( ) C 16.586k for 0.6mhz f o 4mhz. alternatively, use figure 1 to select the value for r t . the maximum operating frequency is also constrained by the minimum on-time and duty cycle. this can be calculated as: f o(max) 6.67 v out v in(max) ? ? ? ? ? ? ? ? mhz ( ) the minimum frequency is limited by leakage and noise coupling due to the large resistance of r t . inductor selection although the inductor does not infuence the operating frequency, the inductor value has a direct effect on ripple current. the inductor ripple current, ? i l , decreases with higher inductance and increases with higher v in or v out . ? i l = v out f o ? l 1C v out v in ? ? ? ? ? ? accepting larger values of ? i l allows the use of low induc- tances, but results in higher output voltage ripple, greater core losses and lower output current capability. a reasonable starting point for setting ripple current is ?i l = 0.35i load(max) , where i load(max) is the maximum current output. the largest ripple, ?i l , occurs at the maxi- mum input voltage. to guarantee that the ripple current stays below a specifed maximum, the inductor value should be chosen according to the following equation: l = v out f o ? ? i l 1C v out v in(max) ? ? ? ? ? ? ? ? the inductor value will also have an effect on burst mode operation. the transition from low current operation begins when the peak inductor current falls below a level set by the burst clamp. lower inductor values result in higher ripple current which causes this to occur at lower load currents. this causes a dip in effciency in the upper range of low current operation. in burst mode operation, lower inductor values will cause the burst frequency to increase. frequency (mhz) 0 r t (k) 60 80 100 1.5 2.5 3.53.0 4.0 3417 f01 40 20 0 0.5 1.0 2.0 120 140 160 4.5
ltc3417a 10 3417afc applica t ions in f or m a t ion inductor core selection different core materials and shapes will change the size/ current relationship of an inductor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. the choice of which style inductor to use often depends more on the price vs size requirements of any radiated feld/emi requirements than on what the ltc3417a requires to operate. table 1 shows some typical surface mount inductors that work well in ltc3417a applications. input capacitor (c in ) selection in continuous mode, the input current of the converter can be approximated by the sum of two square waves with duty cycles of approximately v out1 /v in and v out2 /v in . to prevent large voltage transients, a low equivalent series resistance (esr) input capacitor sized for the maximum rms current must be used. some capacitors have a de-rating spec for maximum rms current. if the capaci - tor being used has this requirement, it is necessary to calculate the maximum rms current. the rms current calculation is different if the part is used in in phase or out of phase. for in phase, there are two different equations: v out1 > v out2 : i rms = 2 ? i 1 ? i 2 ? d2(1C d1) + i 2 2 (d2 C d2 2 ) + i 1 2 (d1C d1 2 ) v out2 > v out1 : i rms = 2 ? i 1 ? i 2 ? d1(1C d2) + i 2 2 (d2 C d2 2 ) + i 1 2 (d1C d1 2 ) where: d1 = v out1 v in and d2 = v out2 v in table 1 manufacturer part number value (h) max dc current (a) dcr dimensions l w h (mm) l1 on out1 toko a920cy-1r5m-d62cb a918cy-1r5m-d62lcb 1.5 1.5 2.8 2.9 0.014 0.018 6 6 2.5 6 6 2 coilcraft do1608c-152ml 1.5 2.6 0.06 6.6 4.5 2.9 sumida cdrh4d22/hp 1r5 1.5 3.9 0.031 5 5 2.4 midcom dup-1813-1r4r 1.4 5.5 0.033 4.3 4.8 3.5 l2 on out2 toko a915ay-2r0m-d53lc 2.0 3.9 0.027 5 5 3 coilcraft do1608c-222ml 2.2 2.3 0.07 6.6 4.5 2.9 sumida cdrh3d16/hp 2r2 cdrh2d18/hp 2r2 2.2 2.2 1.75 1.6 0.047 0.035 4 4 1.8 3.2 3.2 2 midcom dup-1813-2r2r 2.2 3.9 0.047 4.3 4.8 3.5
ltc3417a 11 3417afc applica t ions in f or m a t ion when d1 = d2 then the equation simplifes to: i rms = i 1 + i 2 ( ) d 1C d ( ) or i rms = i 1 + i 2 ( ) v out v in C v out ( ) v in where the maximum average output currents i 1 and i 2 equal the respective peak currents minus half the peak- to-peak ripple currents: i 1 = i lim1 C ? i l1 2 i 2 = i lim2 C ? i l2 2 these formula have a maximum at v in = 2v out , where i rms = (i 1 + i 2 )/2. this simple worst case is commonly used to determine the highest i rms . for out of phase operation, the ripple current can be lower than the in phase current. in the out of phase case, the maximum i rms does not occur when v out1 = v out2 . the maximum typically oc- curs when v out1 C v in /2 = v out2 or when v out2 C v in /2 = v out1 . as a good rule of thumb, the amount of worst case ripple is about 75% of the worst case ripple in the in phase mode. also note that when v out1 = v out2 = v in /2 and i 1 = i 2 , the ripple is zero. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours lifetime. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet the size or height requirements of the design. an additional 0.1f to 1f ceramic capacitor is also recommended on v in for high frequency decoupling, when not using an all ceramic capacitor solution. output capacitor (c out1 and c out2 ) selection the selection of c out1 and c out2 is driven by the required esr to minimize voltage ripple and load step transients. typically, once the esr requirement is satisfed, the capacitance is adequate for fltering. the output ripple ( ? v out ) is determined by: ? v out ? i l esr cout + 1 8 ? f o ? c out ? ? ? ? ? ? where f o = operating frequency, c out = output capacitance and ? i l = ripple current in the inductor. the output ripple is highest at maximum input voltage, since ? i l increases with input voltage. with ? i l = 0.35i load(max) , the output ripple will be less than 100mv at maximum v in and f o = 1mhz with: esr cout < 150m once the esr requirements for c out have been met, the rms current rating generally far exceeds the i ripple(p-p) requirement, except for an all ceramic solution. in surface mount applications, multiple capacitors may have to be paralleled to meet the capacitance, esr or rms current handling requirement of the application. aluminum electrolytic, special polymer, ceramic and dry tantalum capacitors are all available in surface mount packages. the os-con semiconductor dielectric capacitor avail- able from sanyo has the lowest esr(size) product of any aluminum electrolytic at a somewhat higher price. special polymer capacitors, such as sanyo poscap, offer very low esr, but have a lower capacitance density than other types. tantalum capacitors have the highest capacitance density, but it has a larger esr and it is critical that the capacitors are surge tested for use in switching power supplies. an excellent choice is the avx tps series of surface tantalums, available in case heights ranging from 2mm to 4mm. aluminum electrolytic capacitors have a signifcantly larger esr, and are often used in extremely cost-sensitive applications provided that consideration
ltc3417a 12 3417afc applica t ions in f or m a t ion is given to ripple current ratings and long term reliability. ceramic capacitors have the lowest esr and cost but also have the lowest capacitance density, high voltage and temperature coeffcient and exhibit audible piezoelectric effects. in addition, the high q of ceramic capacitors along with trace inductance can lead to signifcant ringing. other capacitor types include the panasonic specialty polymer (sp) capacitors. in most cases, 0.1f to 1f of ceramic capacitors should also be placed close to the ltc3417a in parallel with the main capacitors for high frequency decoupling. ceramic input and output capacitors higher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. because the ltc3417 control loop does not depend on the output capacitors esr for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. when choosing the input and output ceramic capacitors, choose the x5r or x7r dielectric formulations. these dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. great care must be taken when using only ceramic input and output capacitors. when a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the v in pin. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, the ringing at the input can be large enough to damage the part. since the esr of a ceramic capacitor is so low, the input and output capacitor must fulfll a charge storage re- quirement. during a load step, the output capacitor must instantaneously supply the current to support the load until the feedback loop raises the switch current enough to support the load. the time required for the feedback loop to respond is dependent on the compensation com- ponents and the output capacitor size. typically, 3 to 4 cycles are required to respond to a load step, but only in the frst cycle does the output drop linearly. the output droop, v droop , is usually about 2 to 3 times the linear droop of the frst cycle. thus, a good place to start is with the output capacitor size of approximately: c out 2.5 ? i out f o ? v droop more capacitance may be required depending on the duty cycle and load step requirements. in most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance to the supply is very low. a 10f ceramic capacitor is usually enough for these conditions. setting the output voltage the ltc3417a develops a 0.8v reference voltage between the feedback pins, v fb1 and v fb2 , and the signal ground as shown in figure 4. the output voltages are set by two resistive dividers according to the following formulas: v out1 0.8v 1 + r1 r2 ? ? ? ? ? ? v out2 0.8v 1 + r3 r4 ? ? ? ? ? ? keeping the current small (<5a) in these resistors maximizes effciency, but making the current too small may allow stray capacitance to cause noise problems and reduce the phase margin of the error amp loop. to improve the frequency response, a feed-forward ca - pacitor, c f , may also be used. great care should be taken to route the v fb node away from noise sources, such as the inductor or the sw line. soft-start soft-start reduces surge currents from v in by gradu- ally increasing the peak inductor current. power supply sequencing can also be accomplished by controlling the i th pin. the ltc3417a has an internal digital soft-start for each regulator output, which steps up a clamp on
ltc3417a 13 3417afc applica t ions in f or m a t ion figure 2. digital soft-start out1 i th over 1024 clock cycles, as can be seen in figures 2 and 3. as the voltage on i th ramps through its operating range, the internal peak current limit is also ramped at a proportional linear rate. mode selection the sync/mode pin is a multipurpose pin which provides mode selection and frequency synchronization. connect- ing this pin to v in enables burst mode operation for both regulators, which provides the best low current effciency at the cost of a higher output voltage ripple. when sync/ mode is connected to ground, pulse skipping operation is selected for both regulators, which provides the lowest output voltage and current ripple at the cost of low cur - rent effciency. applying a voltage that is more than 1v from either supply results in forced continuous mode for both regulators, which creates a fxed output ripple and allows the sinking of some current (about 1/2 ? i l ). since the switching noise is constant in this mode, it is also the easiest to flter out. in many cases, the output voltage can be simply connected to the sync/mode pin, select - ing the forced continuous mode except at start-up. the ltc3417a can also be synchronized to an external clock signal by the sync/mode pin. the internal oscillator fre- quency should be set to 20% lower than the external clock frequency to ensure adequate slope compensation, since slope compensation is derived from the internal oscillator. during synchronization, the mode is set to pulse skipping figure 3. digital soft-start out2 v in = 3.6v v out = 1.8v r l = 0.9 200s/div i l 1a/div v out 1v/div v run 2v/div v in = 3.6v v out = 2.5v r l = 2 200s/div i l 0.5a/div v out 1v/div v run 2v/div and the top switch turn-on is synchronized to the rising edge of the external clock. when using an external clock, with the phase pin low, the switching of the two channels occur at the edges of the external clock. a 50% duty cycle will therefore produce 180 out-of-phase operation. checking transient response the i th pin compensation allows the transient response to be optimized for a wide range of loads and output capacitors. the availability of the i th pin not only allows optimization of the control loop behavior, but also pro - vides a dc coupled and ac fltered closed-loop response test point. the dc step, rise time, and settling at this test point truly refects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated using the percentage of overshoot seen at this pin or by examining the rise time at this pin. the i th external components shown in the figure 4 circuit will provide an adequate starting point for most applica- tions. the series rc flter sets the dominant pole-zero loop compensation. the values can be modifed slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the fnal pc layout is done and the particular output capacitor type and value have been
ltc3417a 14 3417afc applica t ions in f or m a t ion determined. the output capacitors need to be selected because of various types and values determine the loop feedback factor gain and phase. an output current pulse of 20% to 100% of full load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of overall loop stability without breaking the feedback loop. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out im - mediately shifts by an amount equal to ? i load ? esr cout , where esr cout is the effective series resistance of c out . ? i load also begins to charge or discharge c out generat- ing a feedback error signal used by the regulator to return v out to its steady-state value. during this recovery time, v out can be monitored for overshoot or ringing that would indicate a stability problem. the initial output voltage step may not be within the band- width of the feedback loop, so the standard second order overshoot/dc ratio cannot be used to determine phase margin. the gain of the loop increases with r ith and the bandwidth of the loop increases with decreasing c ith . if r ith is increased by the same factor that c ith is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. in addition, feedforward capacitors, c1 and c2, can be added to improve the high frequency response, as shown in figure 4. capacitor c1 provides phase lead by creating a high frequency zero with r1 which improves the phase margin for the 1.5a sw1 chan- nel. capacitor c2 provides phase lead by creating a high frequency zero with r3 which improves the phase margin for the 1a sw2 channel. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to linear technology application note 76. although a buck regulator is capable of providing the full output current in dropout, it should be noted that as the input voltage v in drops toward v out , the load step capability does decrease due to the decreasing voltage across the inductor. applications that require large load step capabil - ity near dropout should use a different topology such as sepic, zeta, or single inductor, positive buck boost. in some applications, a more severe transient can be caused by switching in loads with large (>1f) input capacitors. the discharged input capacitors are effectively put in paral- lel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem, if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap? controller is designed specifcally for this purpose and usually incorporates cur - rent limiting, short-circuit protection, and soft-starting. effciency considerations the percent effciency of a switching regulator is equal to the output power divided by the input power times 100. it is often useful to analyze individual losses to determine what is limiting the effciency and which change would produce the most improvement. percent effciency can be expressed as: % effciency = 100% C (p1+ p2 + p3 +) where p1, p2, etc. are the individual losses as a percent - age of input power. although all dissipative elements in the circuit produce losses, four main sources account for most of the losses in ltc3417a circuits: 1) ltc3417a i s current, 2) switching losses, 3) i 2 r losses, 4) other losses. 1) the i s current is the dc supply current given in the elec- trical characteristics which excludes mosfet driver and control currents. i s current results in a small (< 0.1%) loss that increases with v in , even at no load. 2) the switching current is the sum of the mosfet driver and control currents. the mosfet driver current re- sults from switching the gate capacitance of the power mosfet s. each time a mosfet gate is switched from
ltc3417a 15 3417afc applica t ions in f or m a t ion low to high to low again, a packet of charge moves from v in to ground. the resulting charge over the switching period is a current out of v in that is typically much larger than the dc bias current. the gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 3) i 2 r losses are calculated from the dc resistances of the internal switches, r sw , and the external inductor, r l . in continuous mode, the average output current fowing through inductor l is chopped between the internal top and bottom switches. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on) top)(dc) + (r ds(on) bot)(1 C dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus, to obtain i 2 r losses: i 2 r losses = i out 2 (r sw + r l ) where r l is the resistance of the inductor. 4) other hidden losses such as copper trace and internal battery resistances can account for additional effciency degradations in portable systems. it is very important to include these system level losses in the design of a system. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr cout at the switching frequency. other losses including diode conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. thermal considerations the ltc3417a requires the package exposed pad (pgnd2/gndd pin) to be well soldered to the pc board. this gives the dfn and tssop packages exceptional thermal properties, compared to similar packages of this size, making it diffcult in normal operation to exceed the maximum junction temperature of the part. in a majority of applications, the ltc3417a does not dissipate much heat due to its high effciency. however, in applications where the ltc3417a is running at high ambient tem - perature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 150c, both switches in both regulators will be turned off and the sw nodes will become high impedance. to prevent the ltc3417a from exceeding its maximum junction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the temperature rise is given by: t rise = p d ? ja where p d is the power dissipated by the regulator and ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t rise + t ambient as an example, consider the case when the ltc3417a is in dropout in both regulators at an input voltage of 3.3v with load currents of 1.5a and 1a. from the typical per - formance characteristics graph of switch resistance, the r ds(on) resistance of the 1.5a p-channel switch is 0.09 and the r ds(on) of the 1a p-channel switch is 0.163. the power dissipated by the part is: pd = i 1 2 ? r ds(on)1 + i 2 2 ? r ds(on)2 pd = 1.5 2 ? 0.09 + 1 2 ? 0.163 pd = 366mw the dfn package junction-to-ambient thermal resistance, ja , is about 43c/w. therefore, the junction temperature of the regulator operating in a 70c ambient temperature is approximately: t j = 0.366 ? 43 + 70 t j = 85.7c
ltc3417a 16 3417afc applica t ions in f or m a t ion remembering that the above junction temperature is obtained from an r ds(on) at 25c, we might recalculate the junction temperature based on a higher r ds(on) since it increases with temperature. however, we can safely as - sume that the actual junction temperature will not exceed the absolute maximum junction temperature of 125c. design example as a design example, consider using the ltc3417a in a portable application with a li-ion battery. the battery provides a v in from 2.8v to 4.2v. one load requires 1.8v at 1.5a in active mode, and 1ma in standby mode. the other load requires 2.5v at 1a in active mode, and 500a in standby mode. since both loads still need power in standby, burst mode operation is selected for good low load effciency (sync/mode = v in ). first, determine what frequency should be used. higher frequency results in a lower inductor value for a given ?i l (?i l is estimated as 0.35i load(max) ). reasonable values for wire wound surface mount inductors are usually in the range of 1h to 10h. converter output i load(max) ?i l sw1 1.5a 525ma sw2 1a 350ma using the 1.5mhz frequency setting (freq = v in ), we get the following equations for l1 and l2: l1 = 1.8v 1.5mhz ? 525ma 1C 1.8v 4.2v ? ? ? ? ? ? = 1.3h use 1.5h. l2 = 2.5v 1.5mhz ? 350ma 1C 2.5v 4.2v ? ? ? ? ? ? = 1.9h use 2.2h. c out selection is based on load step droop instead of esr requirements. for a 2.5% output droop: c out1 = 2.5 ? 1.5a 1.5mhz 5% ? 1.8v ( ) = 28f c out2 = 2.5 ? 1a 1.5mhz 5% ? 2.5v ( ) = 13f the closest standard values are 47f and 22f. the output voltages can now be programmed by choos- ing the values of r1, r2, r3, and r4. to maintain high effciency, the current in these resistors should be kept small. choosing 2a with the 0.8v feedback voltages makes r2 and r4 equal to 400k. a close standard 1% resistor is 412k. this then makes r1 = 515k. a close standard 1% is 511k. similarily, with r4 at 412k, r3 is equal to 875k. a close 1% resistor is 866k. the compensation should be optimized for these com- ponents by examining the load step response, but a good place to start for the ltc3417a is with a 5.9k and 2200pf flter on i th1 and 2.87k and 6800pf on i th2 . the output capacitor may need to be increased depending on the actual undershoot during a load step. the pgood pin is a common drain output and requires a pull-up resistor. a 100k resistor is used for adequate speed. figure 4 shows a complete schematic for this design.
ltc3417a 17 3417afc applica t ions in f or m a t ion out1 effciency vs load current figure 4. 1.8v at 1.5a/2.5v at 1a step-down regulators sync/mode sw1 run1 v fb1 phase i th1 pgood sw2 run2 v fb2 freq i th2 v in1 ltc3417a gnda exposed pad gndd v in2 c in 10f c in1 0.1f c in2 0.1f l1 1.5h l2 2.2h c1 22pf r1 511k c2 22pf r3 866k v in v in v in r7 100k r2 412k r4 412k c out2 22f r5 5.9k r6 2.87k c3 2200pf c4 6800pf 3417 f04 c out1 47f v out1 1.8v 1.5a v out2 2.5v 1a v in 2.25v to 5.5v l1: midcom dus-5121-1r5r c out1 : kemet c1210c226k8pac l2: midcom dus-5121-2r2r c out2 , c in : kemet c1206c106k4pac load current (a) 80 efficiency (%) power loss (w) 90 100 75 85 95 0.001 0.1 1 10 3417 f04a 70 0.1 10 0.01 1 0.001 0.01 v in = 3.6v v out = 1.8v freq = 1mhz refer to figure 4 efficiency power loss
ltc3417a 18 3417afc applica t ions in f or m a t ion board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3417a. these items are also illustrated graphically in the layout diagram of figure 5. check the following in your layout. 1 . does the capacitor c in connect to the power v in1 (pin 2), v in2 (pin 8), and pgnd2/gndd (pin 17) as close as possible (dfn package)? it may be necessary to split c in into two capacitors. this capacitor provides the ac current to the internal power mosfets and their drivers. 2. are the c out1 , l1 and c out2 , l2 closely connected? the (C) plate of c out1 returns current to pgnd1, and the (C) plate of c out2 returns current to the pgnd2/gndd and the (C) plate of c in . 3. the resistor divider, r1 and r2, must be connected between the (+) plate of c out1 and a ground line ter - minated near gnda. the resistor divider, r3 and r4, must be connected between the (+) plate of c out2 and a ground line terminated near gnda. the feedback signals v fb1 and v fb2 should be routed away from noise components and traces, such as the sw lines, and its trace should be minimized. 4. keep sensitive components away from the sw pins. the input capacitor c in , the compensation capacitors c c1 , c c2 , c ith1 and c ith2 and all resistors r1, r2, r3, r4, r ith1 and r ith2 should be routed away from the sw traces and the inductors l1 and l2. 5. a ground plane is preferred, but if not available, keep the signal and power grounds segregated with small signal components returning to the gnda pin at one point which is then connected to the pgnd2/gndd pin. 6. flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. these copper areas should be connected to one of the input supplies. figure 5. layout guideline v in2 pgnd2/ exposed pad v in1 pgnd1 sw1 v fb1 i th1 freq run1 sync/mode ltc3417a gndd v in v in v in c in 10f c in2 0.1f c in1 0.1f c out2 v out2 c out1 v out1 l2 l1 c c2 c c1 r3 r4 r ith2 c ith2 c ith1 r8 r1 r2 r ith1 r7 star to gnda star to gnda gnda sw2 v fb2 i th2 pgood run2 phase
ltc3417a 19 3417afc p ackage descrip t ion dhc package 16-lead plastic dfn (5mm 3mm) (reference ltc dwg # 05-08-1706) 3.00 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wjed-1) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 4.40 0.10 (2 sides) 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dhc16) dfn 1103 0.25 0.05 pin 1 notch 0.50 bsc 4.40 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.20 0.05 0.50 bsc 0.65 0.05 3.50 0.05 package outline 0.25 0.05
ltc3417a 20 3417afc fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev i) exposed pad variation ca p ackage descrip t ion fe20 (ca) tssop rev i 0211 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 111214 13 6.40 ? 6.60* (.252 ? .260) 4.95 (.195) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 4.95 (.195) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev i) exposed pad variation ca
ltc3417a 21 3417afc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number c 3/11 changed 100a to 125a in the last paragraph of the description section. 1 (revision history begins at rev c)
ltc3417a 22 3417afc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0311 rev c ? printed in usa rela t e d par t s part number description comments ltc3404 600ma (i out ), 1.4mhz, synchronous step-down dc/dc converter 95% effciency, v in : 2.7v to 6v, v out(min) = 0.8v, i q = 10a, i sd < 1a, ms8 package ltc3405/ltc3405a 300ma (i out ), 1.5mhz, synchronous step-down dc/dc converters 95% effciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 20a, i sd < 1a, thinsot? package ltc3406/ltc3406b 600ma (i out ), 1.5mhz, synchronous step-down dc/dc converters 96% effciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 20a, i sd < 1a, thinsot package ltc3407 dual 600ma (i out ), 1.5mhz, synchronous step-down dc/dc converter 95% effciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd < 1a, mse/dfn packages ltc3407-2 dual 800ma (i out ), 2.25mhz, synchronous step-down dc/dc converter 95% effciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd < 1a, mse/dfn packages ltc3409 600ma (i out ), low v in (1.6v to 5.5v), synchronous step-down dc/dc converter 95% effciency, v in : 1.6v to 5.5v, v out(min) = 0.6v, i q = 65a, i sd < 1a, dfn packages ltc3410/ltc3410b 300ma (i out ), 2.25mhz, synchronous step-down dc/dc converter 95% effciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 26a, i sd < 1a, sc70 packages ltc3411 1.25a (i out ), 4mhz, synchronous step-down dc/dc converter 95% effciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60a, i sd < 1a, ms package ltc3412 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% effciency, v in : 2.5v to 5.5v, v out(min) = 0.8v, i q = 60a, i sd < 1a, tssop16e package ltc3413 3a (i out sink/source), 2mhz, monolithic synchronous regulator for ddr/qdr memory termination 90% effciency, v in : 2.25v to 5.5v, v out(min) = v ref /2, i q = 280a, i sd < 1a, tssop16e package ltc3414 4a (i out ), 4mhz, synchronous step-down dc/dc converter 95% effciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 64a, i sd < 1a, tssop20e package ltc3416 4a (i out ), 4mhz, synchronous step-down dc/dc converter with tracking 95% effciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 64a, i sd < 1a, tssop20e package ltc3417 dual 1.4a/800ma (i out ) 4mhz synchronous step-down dc/dc converter 95% effciency, v in : 2.25v to 5v, v out(min) = 0.8v, i q = 125a, i sd < 1a, dfn, tssop20e packages ltc3418 8a (i out ), 4mhz, synchronous step-down dc/dc converter 95% effciency, v in : 2.25v to 5.5v, v out(min) = 0.8v, i q = 380a, i sd < 1a, qfn package ltc3440 600ma (i out ), 2mhz, synchronous buck-boost dc/dc converter 95% effciency, v in : 2.5v to 5.5v, v out(min) = 2.4v, i q = 25a, i sd < 1a, ms/dfn packages ltc3441 600ma (i out ), 2mhz, synchronous buck-boost dc/dc converter 95% effciency, v in : 2.5v to 5.5v, v out(min) = 2.4v, i q = 25a, i sd < 1a, dfn package ltc3443 1.2a (i out ), 600khz, synchronous buck-boost dc/dc converter 95% effciency, v in : 2.4v to 5.5v, v out(min) = 2.4v, i q = 28a, i sd < 1a, ms package ltc3448 1.5mhz/2.25mhz, 600ma synchronous step-down dc/dc converter with ldo mode 96% effciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 32a, i sd < 1a, dfn/ms8e ltc3548 dual 800ma and 400ma (i out ), 2.25mhz, synchronous step-down dc/dc converter 95% effciency, v in : 2.5v to 5.5v, v out(min) = 0.6v, i q = 40a, i sd < 1a, mse/dfn packages

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